By Rezaur Rahman
Intel® Xeon Phi™ Coprocessor structure and instruments: The advisor for software builders offers builders a accomplished creation and in-depth examine the Intel Xeon Phi coprocessor structure and the corresponding parallel facts constitution instruments and algorithms utilized in some of the technical computing functions for which it's appropriate. It additionally examines the resource code-level optimizations that may be played to use the strong positive factors of the processor.
Xeon Phi is on the middle of world’s quickest advertisement supercomputer, which because of the hugely parallel computing functions of Intel Xeon Phi processors coupled with Xeon Phi coprocessors attained 33.86 teraflops of benchmark functionality in 2013. Extracting such stellar functionality in real-world purposes calls for a worldly realizing of the advanced interplay between parts, Xeon Phi cores, and the functions working on them.
In this publication, Rezaur Rahman, an Intel chief within the improvement of the Xeon Phi coprocessor and the optimization of its functions, offers and information all of the beneficial properties of Xeon Phi middle layout which are correct to the perform of program builders, corresponding to its vector devices, multithreading, cache hierarchy, and host-to-coprocessor verbal exchange channels. construction in this starting place, he exhibits builders how you can clear up real-world technical computing difficulties via settling on, deploying, and optimizing the to be had algorithms and information constitution possible choices matching Xeon Phi’s features. From Rahman’s sensible descriptions and large code examples, the reader will achieve a operating wisdom of the Xeon Phi vector guide set and the Xeon Phi microarchitecture wherein cores execute 512-bit guideline streams in parallel.
What you’ll learn
How to calculate theoretical Gigaflops and bandwidth numbers at the and degree them via code segment
How to estimate latencies in fetching facts from various cache hierarchies, together with reminiscence subsystems
How to degree PCIe bus bandwidth among the host and coprocessor
How to use strength administration and reliability gains outfitted into the hardware
How to pick and manage the easiest instruments to music specific Xeon Phi applications
Algorithms and knowledge constructions for optimizing Xeon Phi performance
Case experiences of real-world Xeon Phi technical computing purposes in molecular dynamics and fiscal simulations
Who this e-book is for
This e-book is for builders wishing to layout and improve technical computing purposes to accomplish the top functionality to be had within the Intel Xeon Phi coprocessor undefined. It offers a fantastic base at the coprocessor structure, in addition to set of rules and information constitution case reviews for Xeon Phi coprocessor. The booklet can also be of curiosity to scholars and practitioners in computing device engineering as a case research for vastly parallel center microarchitecture of recent day processors.